Every new generation of integrated circuits with increased operating frequency, performance and the higher level of large scale integration have underscored the need for the integrated circuit packaging to meet the high speed signaling requirements of the integrated circuits. Modern consumer electronics, such as smart phones, personal digital assistants, and location based services devices, as well as enterprise electronics, such as servers and storage arrays, are packing more integrated circuits into an ever shrinking physical space with expectations for decreasing cost. Contemporary consumer electronics expose integrated circuits and packages to more demanding and sometimes new environmental conditions, such as cold, heat, and humidity requiring integrated circuit packages to provide robust thermal management structures.
As more functions are packed into the integrated circuits and more integrated circuits into the package, the packaged integrated circuits reliably provide the high performance across specified environmental conditions. The integrated circuits bare a portion of performance assurance over various conditions. The integrated circuit package also bares a portion of the performance assurance and in some case more than the integrated circuits.
Numerous technologies have been developed to meet these requirements. Some of the research and development strategies focus on new package technologies while others focus on improving the existing and mature package technologies. Research and development in the existing package technologies may take a myriad of different directions.
One proven way to reduce cost is to use package technologies with existing manufacturing methods and equipments. Paradoxically, the reuse of existing manufacturing processes does not typically result in the reduction of package dimensions. Existing packaging technologies struggle to cost effectively meet the ever demanding integration of today's integrated circuits and packages.
In response to the demands for improved packaging, many innovative package designs have been conceived and brought to market. The multi-chip package has achieved a prominent role in reducing the board space. Numerous package approaches stack multiple integrated circuits, package level stacking, or package-on-package (POP). Known-good-die KGD and assembly process yields are not an issue since each package can be tested prior to assembly, allowing KGD to be used in assembling the stack. But stacking integrated devices, package-on-package, or a combination thereof have system level difficulties, such as increased package height composed of two ordinary packages or package structures not optimal for high performance integrated circuits.
Thus, a need still remains for a multichip package system providing low cost manufacturing, improved yields, increased electrical performance, reduced integrated circuit package dimensions, and integration configurations. In view of the ever-increasing need to save costs and improve efficiencies, it is more and more critical that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.